--- title: "High Bandwidth Flash: Inside the First HBF Standard from SK hynix and Sandisk" slug: high-bandwidth-flash-hbf-first-standard-2026 category: tech category_label: "Tech" author: "BrainWavePost Staff" date: 2026-08-05 tags: ["HBF", "SK hynix", "Sandisk", "HBM", "NAND", "AI infrastructure", "FMS 2026", "OCP", "UCIe"] read_time_minutes: 9 canonical_url: https://brainwavepost.com/article/high-bandwidth-flash-hbf-first-standard-2026 source: BrainWavePost --- # High Bandwidth Flash: Inside the First HBF Standard from SK hynix and Sandisk *Tech · 2026-08-05 · BrainWavePost Staff · 9 min read* > SK hynix and Sandisk have published the first technical specification for High Bandwidth Flash — up to 512GB per stack, 0.4 to 3.0 TB/s, connected over UCIe. Here is what the standard actually defines, sourced from the companies' own announcements. > **How this article is sourced** _(info)_ > > Every specification figure below comes from the SK hynix Newsroom press release and the Sandisk newsroom announcement of the OCP technical specification, cross-checked against trade coverage from SDxCentral, The Korea Times, The Elec and Seoul Economic Daily. Numbered citations link to the originals. Nothing here is estimated, and forward-looking commercialisation timing is attributed to the outlet that reported it. [1][2][3][4][5][6] On 3–4 August 2026, Sandisk Corporation and SK hynix announced the release of the first High Bandwidth Flash (HBF) technical specification through the Open Compute Project (OCP). [1][2] The announcement was timed to the opening of FMS (Future of Memory and Storage) 2026 at the Santa Clara Convention Center, which ran 4–6 August. [1][3] The specification arrives roughly six months after the HBF standardisation workstream began in February 2026, itself following an initial standardisation partnership between the two companies announced in August 2025. [1][2] Google and Tenstorrent joined the consortium during the standardisation process and, per Sandisk, contributed to technology validation and establishing the standard. [1][2] - **512GB** — maximum capacity per HBF device in the first spec [1][3][4] - **0.4–3.0 TB/s** — bandwidth across three defined grades [3][4][5] - **8- or 16-high** — the two defined NAND die stack configurations [3][4] ## What HBF is, in one paragraph HBF is a new memory layer that sits between HBM and conventional SSD storage inside an AI system. [1][4] It borrows the vertical stacking and advanced packaging ideas that made HBM possible, but stacks NAND flash instead of DRAM — trading some latency for far more capacity at a much lower cost per gigabyte. [1][5] Because many NAND layers operate simultaneously, aggregate bandwidth rises well above what a single NAND device or an SSD can deliver, which is how HBF compensates for NAND's slower intrinsic operating speed. [4][6] SK hynix frames the motivation directly: as AI inference drives a surge in the volume of data that must be processed, HBF is positioned as a technology that addresses bandwidth and capacity scalability at the same time. [1] The company describes the resulting design pattern as 'Tiered Memory' — the theme of its FMS 2026 keynote. [1] ## What the specification actually pins down This is a technical specification, not a product launch. According to both companies and the reporting that followed, the document defines four things: [1][2][3][4] - Capacity and stack configurations — two configurations built from 8-high or 16-high NAND die stacks, supporting capacities up to 512GB. [1][3][4] - Bandwidth grades — three tiers, ranging from roughly 0.4 TB/s at the low end to 3.0 TB/s at the top, so that a device holding model weights can be specified differently from one streaming KV cache. [3][4][5] - Interface and electrical characteristics, plus reliability and packaging guidance for the die stack. [2][4] - Software guidelines for read and write (data input/output) operations. [2][4] The interconnect choice is arguably the most consequential detail. HBF connects to logic processors over Universal Chiplet Interconnect Express (UCIe), the open chiplet interface — meaning a GPU, CPU or custom accelerator that already speaks UCIe has a defined path to HBF rather than needing a proprietary controller. [3][4][5] > **Why an open standard matters here** _(tip)_ > > In the semiconductor industry, publishing a technical standard is generally treated as the first step toward building an ecosystem — it lets materials, equipment and controller vendors design against a common target before silicon ships. [4] Sandisk describes the spec as giving designers of AI inference systems and accelerators 'a common technical framework' for adopting HBF. [2] ## How it compares with HBM Both companies are explicit that HBF is not a replacement for HBM. [2][5] HBM keeps the latency-sensitive work; HBF holds the bulk of the data close to compute. [5] For scale, Seoul Economic Daily compared the HBF spec against HBM4E (64GB at 4 TB/s), which it reported is due next year: on that comparison HBF offers roughly eight times the capacity while retaining up to about 75% of the bandwidth. [6] The economic argument behind HBF, which Sandisk has made since first describing the technology in February 2025, is that DRAM-based HBM cannot scale indefinitely either physically or economically, and that pairing HBM-style stacking with non-volatile NAND buys capacity at a comparable price point. [5] SDxCentral also reports that Google engineers have credited the approach with the potential to provide roughly ten times the memory capacity per node for inference workloads. [5] ## Quotes from the companies > AI inference is creating a new set of memory requirements, and HBF technology is designed to meet that moment. This specification helps give system designers a practical path to bring high-capacity, high-bandwidth memory closer to compute, while enabling more flexible architectures. > > — Alper Ilkbahar, Chief Technology Officer, Sandisk [2] > With the rapid spread of AI applications, we are at a point where overall data processing structures must be redesigned. Through HBF, SK hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency. > > — Kim Chun-sung, EVP and Head of Solution Development, SK hynix [5] ## What else SK hynix showed at FMS 2026 Alongside the specification, SK hynix used its FMS 2026 booth to unveil its tenth-generation (V10) 375-layer 4D NAND for the first time, which the company says offers a 2.5 times increase in power efficiency. [1] Its programme also included an opening-day keynote by Executive Vice President Kim Chun-sung and Vice President Kang Uk-song on tiered-memory approaches to next-generation AI infrastructure, and a panel titled 'Breaking the Memory Wall with HBF' held with Google DeepMind and Sandisk. [1] ## What is still unknown A published standard is not a shipping product, and the announcements do not include pricing, sampling dates, or named production designs. Seoul Economic Daily reports an industry expectation that HBF will be commercialised around 2030 — that timing is an industry expectation reported by the outlet, not a company commitment. [6] Real-world latency behaviour, endurance under write-heavy inference patterns, and how systems software will tier data between HBM and HBF are all left to implementers by a specification of this kind. ## Sources and further reading - [1] SK hynix Newsroom — 'SK hynix Unveils First HBF Standard Specifications with Sandisk, Presenting AI Memory Solutions at FMS 2026' (4 August 2026): https://news.skhynix.com/en/hbf-at-fms-2026/ - [2] Sandisk Newsroom — 'Sandisk and SK hynix Advance Global Standardization of High Bandwidth Flash with Release of First OCP Technical Specification' (3 August 2026): https://www.sandisk.com/company/newsroom/press-releases/2026/2026-08-03-Sandisk-and-sk-hynix-advance-global-standardization-of-hbf - [3] The Korea Times — 'SK hynix, Sandisk unveil standards for high-bandwidth flash memory' (4 August 2026): https://www.koreatimes.co.kr/business/tech-science/20260804/sk-hynix-sandisk-unveil-standards-for-high-bandwidth-flash-memory - [4] The Elec — 'SK hynix and Sandisk Unveil First HBF Standard, Supporting Up to 512GB Capacity' (5 August 2026): https://www.thelec.net/news/articleView.html?idxno=12793 - [5] SDxCentral — 'SK Hynix, Sandisk unveil first standard for high-bandwidth flash', by Ben Wodecki (4 August 2026): https://www.sdxcentral.com/news/sk-hynix-sandisk-unveil-first-standard-for-high-bandwidth-flash/ - [6] Seoul Economic Daily — 'SK hynix Moves to Seize HBF Standard for Next-Generation NAND' (4 August 2026): https://en.sedaily.com/finance/2026/08/04/sk-hynix-moves-to-seize-hbf-standard-for-next-generation - [7] Open Compute Project — the standards body through which the HBF specification was published: https://www.opencompute.org/ - [8] UCIe Consortium — the Universal Chiplet Interconnect Express standard used to connect HBF to logic processors: https://www.uciexpress.org/ --- _Canonical article: [https://brainwavepost.com/article/high-bandwidth-flash-hbf-first-standard-2026](https://brainwavepost.com/article/high-bandwidth-flash-hbf-first-standard-2026) — © BrainWavePost. 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